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INTEGRATED CIRCUITS
DATA SHEET
74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Product specification Supersedes data of 1998 Jun 04 2003 Jun 25
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
FEATURES * 8-bit serial input * 8-bit serial or parallel output * Storage register with 3-state outputs * Shift register with direct clear * 100 MHz (typical) shift out frequency * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. APPLICATIONS * Serial-to-parallel data conversion * Remote control holding register. DESCRIPTION
74HC595; 74HCT595
The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted on the positive-going transitions of the SH_CP input. The data in each register is transferred to the storage register on a positive-going transition of the ST_CP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7') for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay SH_CP to Q7' SH_CP to Qn MR to Q7' fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. For 74HC595 the condition is VI = GND to VCC. For 74HCT595 the condition is VI = GND to VCC - 1.5 V. 2003 Jun 25 2 maximum clock frequency SH_CP and ST_CP input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS 74HC CL = 50 pF; VCC = 4.5 V 19 20 100 100 3.5 115 25 24 52 57 3.5 130 ns ns ns MHz pF pF 74HCT UNIT
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
FUNCTION TABLE See note 1. INPUT SH_CP ST_CP X X X X X X OE L L H L MR L L L H DS X X X H OUTPUT
74HC595; 74HCT595
FUNCTION Q7' L L L Q6' Qn n.c. L Z n.c. a LOW level on MR only affects the shift registers empty shift register loaded into storage register shift register clear; parallel outputs in high-impedance OFF-state logic high level shifted into shift register stage 0; contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6') appears on the serial output (Q7') contents of shift register stages (internal Qn') are transferred to the storage register and parallel output stages contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages
X
L
H
X
n.c.
Qn'
L
H
X
Q6'
Qn'
Note 1. H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; = HIGH-to-LOW transition; Z = high-impedance OFF-state; n.c. = no change; X = don't care. ORDERING INFORMATION PACKAGE TYPE NUMBER 74HC595N 74HCT595N 74HC595D 74HCT595D 74HC595DB 74HCT595DB 74HC595PW 74HCT595PW 74HC595BQ 74HCT595BQ TEMPERATURE RANGE -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C PINS 16 16 16 16 16 16 16 16 16 16 PACKAGE DIP16 DIP16 SO16 SO16 SSOP16 SSOP16 TSSOP16 TSSOP16 DHVQFN16 DHVQFN16 MATERIAL plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic CODE SOT38-4 SOT38-4 SOT109-1 SOT109-1 SOT338-1 SOT338-1 SOT403-1 SOT403-1 SOT763-1 SOT763-1
2003 Jun 25
3
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND Q7' MR SH_CP ST_CP OE DS Q0 VCC parallel data output parallel data output parallel data output parallel data output parallel data output parallel data output parallel data output ground (0 V) serial data output master reset (active LOW) shift register clock input storage register clock input output enable (active LOW) serial data input parallel data output positive supply voltage
74HC595; 74HCT595
DESCRIPTION
handbook, halfpage
handbook, halfpage
Q1 1
VCC 16 15 14 13 Q0 DS OE ST_CP SH_CP MR
Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 2 3 4
16 VCC 15 Q0
Q2 Q3
2 3 4
14 DS 13 OE
Q4 Q5 Q6
595
5 6 7 12 ST_CP 11 SH_CP
GND(1)
5 6 7 8 Top view GND 9 Q7'
MBL893
12 11 10
10 MR 9
MLA001
GND 8
Q7'
Q7
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig.1
Pin configuration DIP16, SO16 and (T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
2003 Jun 25
4
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
handbook, halfpage
11
12 9 15 1 2 3 4 5 6 7
handbook, halfpage 13
OE
EN3 C2 R SRG8 C1/ 1D 2D 3 15 1 2 3 4 5 6 7 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7'
SH_CP ST_CP Q7' Q0 Q1 Q2 14 DS Q3 Q4 Q5 Q6 Q7 MR 10 OE 13
MLA002
ST_CP MR SH_CP DS
12 10 11 14
MSA698
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
handbook, full pagewidth
14
DS 8-STAGE SHIFT REGISTER
11 SH_CP 10 MR
Q7' ST_CP
9
12
8-BIT STORAGE REGISTER
Q0 Q1 Q2 Q3 13 OE 3-STATE OUTPUTS Q4 Q5 Q6 Q7
15 1 2 3 4 5 6 7
MLA003
Fig.5 Functional diagram.
2003 Jun 25
5
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
handbook, full pagewidth
STAGE 0 D FF0 CP R Q D
STAGES 1 to 6 Q
STAGE 7 D FF7 CP R Q Q7'
DS
SH_CP MR
D CP
Q
D CP
Q
LATCH
LATCH
ST_CP OE
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
MLA010
Fig.6 Logic diagram.
2003 Jun 25
6
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
handbook, full pagewidth SH_CP
DS
ST_CP
MR
OE
Q0 high-impedance OFF-state Q1
Q6
Q7
Q7'
MLA005-1
Fig.6 Timing diagram.
2003 Jun 25
7
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
RECOMMENDED OPERATING CONDITIONS 74HC SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage ambient temperature input rise and fall time VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CONDITIONS MIN. 2.0 0 0 -40 - - - TYP. 5.0 - - - - 6.0 - MAX. 6.0 VCC VCC +125 1000 500 400
74HC595; 74HCT595
74HCT UNIT MIN. 4.5 0 0 -40 - - - TYP. 5.0 - - - - 6.0 - MAX. 5.5 VCC VCC +125 - 500 - V V V C ns ns ns
LIMITED VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK IOK IO PARAMETER supply voltage input diode current output diode current output source or sink current VI < -0.5 V to VI > VCC + 0.5 V VO < -0.5 V to VO > VCC + 0.5 V VO = -0.5 V to VCC + 0.5 V Q7' standard output Qn bus driver outputs ICC, IGND Tstg Ptot Note 1. For DIP16 packages: above 70 C derate linearly with 12 mW/K. For SO16 packages: above 70 C derate linearly with 8 mW/K. For SSOP16 packages: above 60 C derate linearly with 5.5 mW/K. For TSSOP16 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C derate linearly with 4.5 mW/K. VCC or GND current storage temperature power dissipation Tamb = -40 to +125 C; note 1 - - - -65 - 25 35 70 +150 500 mA mA mA C mW CONDITIONS MIN. -0.5 - - MAX. +7.0 20 20 UNIT V mA mA
2003 Jun 25
8
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
DC CHARACTERISTICS
74HC595; 74HCT595
Type 74HC At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C; note 1 VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = -20 A 2.0 4.5 6.0 Q7' standard output IO = -4.0 mA IO = -5.2 mA Qn bus driver outputs IO = -6.0 mA IO = -7.8 mA VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 A 2.0 4.5 6.0 Q7' standard output IO = 4.0 mA IO = 5.2 mA Qn bus driver outputs IO = 6.0 mA IO = 7.8 mA ILI IOZ ICC input leakage current 3-state output OFF-state current quiescent supply current VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 4.5 6.0 6.0 6.0 6.0 - - - - - 0.16 0.16 - - - 0.33 0.33 1.0 5.0 80 V V A A A 4.5 6.0 - - 0.15 0.16 0.33 0.33 V V - - - 0 0 0 0.1 0.1 0.1 V V V 4.5 6.0 3.84 5.34 4.32 5.81 - - V V 4.5 6.0 3.84 5.34 4.32 5.81 - - V V 1.9 4.4 5.9 2.0 4.5 6.0 - - - V V V 1.5 3.15 4.2 - - - 1.2 2.4 3.2 0.8 2.1 2.8 - - - 0.5 1.35 1.8 V V V V V V VCC (V) MIN. TYP. MAX. UNIT
2003 Jun 25
9
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +125 C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = -20 A 2.0 4.5 6.0 Q7' standard output IO = -4.0 mA IO = -5.2 mA Qn bus driver outputs IO = -6.0 mA IO = -7.8 mA VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 A Q7' standard output IO = 4.0 mA Qn bus driver outputs IO = 6.0 mA ILI IOZ ICC Note 1. All typical values are measured at Tamb = 25 C. input leakage current 3-state output OFF-state current quiescent supply current VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 4.5 5.5 5.5 5.5 - - - - 4.5 - 4.5 - 4.5 6.0 3.7 5.2 4.5 6.0 3.7 5.2 1.9 4.4 5.9 1.5 3.15 4.2 - - - VCC (V)
74HC595; 74HCT595
MIN.
TYP.
MAX.
UNIT
- - - - - -
- - - 0.5 1.35 1.8
V V V V V V
- - - - - - -
- - - - - - -
V V V V V V V
- - - - - -
0.1 0.4 0.4 1.0 10.0 160
V V V A A A
2003 Jun 25
10
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
Type 74HCT At recommended operating conditions; voltages are referenced to GND (ground = 0 V); tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C; note 1 VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL all outputs IO = -20 A Q7' standard output IO = -4.0 mA Qn bus driver outputs IO = -6.0 mA VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 A Q7' standard output IO = 4.0 mA Qn bus driver outputs IO = 6.0 mA ILI IOZ ICC ICC input leakage current 3-state output OFF-state current quiescent supply current additional supply current per input VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 VI = VCC - 2.1 V; IO = 0; note 2 4.5 5.5 5.5 5.5 4.5 to 5.5 - - - - - 0.16 - - - 100 0.33 1.0 5.0 80 450 V A A A A 4.5 - 0.15 0.33 V 4.5 - 0 0.33 V 4.5 3.7 4.32 - V 4.5 3.84 4.32 - V 4.5 4.4 4.5 - V 4.5 to 5.5 4.5 to 5.5 2.0 - 1.6 1.2 - 0.8 V V VCC (V) MIN. TYP. MAX. UNIT
2003 Jun 25
11
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +125 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL all outputs IO = -20 A Q7' standard output IO = -4.0 mA Qn bus driver outputs IO = -6.0 mA VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 A Q7' standard output IO = 4.0 mA Qn bus driver outputs IO = 6.0 mA ILI IOZ ICC ICC Notes 1. All typical values are measured at Tamb = 25 C. input leakage current 3-state output OFF-state current quiescent supply current additional supply current per input VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 VI = VCC - 2.1 V; IO = 0; note 2 4.5 5.5 5.5 5.5 4.5 to 5.5 - - - - - 4.5 - 4.5 - 4.5 3.7 4.5 3.7 4.5 4.4 4.5 to 5.5 4.5 to 5.5 2.0 - VCC (V)
74HC595; 74HCT595
MIN.
TYP.
MAX.
UNIT
- -
- 0.8
V V
- - -
- - -
V V V
- - - - - - -
0.1 0.4 0.4 1.0 10.0 160 490
V V V A A A A
2. The value of additional quiescent supply current (ICC) for a unit load of 1 is given here. To determine ICC per input, multiply this value by the unit load coefficient per input pin: a. pin DS: 0.25 b. pins MR, SH_CP, ST_CP and OE: 1.50.
2003 Jun 25
12
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
AC CHARACTERISTICS Family 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL Tamb = 25 C tPHL/tPLH propagation delay SH_CP to Q7' see Fig.7 2.0 4.5 6.0 propagation delay ST_CP to Qn see Fig.8 2.0 4.5 6.0 tPHL propagation delay MR to Q7' see Fig.10 2.0 4.5 6.0 tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 4.5 6.0 tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 4.5 6.0 tW shift clock pulse width HIGH or LOW see Fig.7 2.0 4.5 6.0 storage clock pulse width HIGH or LOW see Fig.8 2.0 4.5 6.0 master reset pulse width LOW see Fig.10 2.0 4.5 6.0 tsu set-up time DS to SH_CP see Fig.9 2.0 4.5 6.0 set-up time SH_CP to ST_CP see Fig.8 2.0 4.5 6.0 th hold time DS to SH_CP see Fig.9 2.0 4.5 6.0 - - - - - - - - - - - - - - - 75 15 13 75 15 13 75 15 13 50 10 9.0 75 15 13 +3 +3 +3 PARAMETER WAVEFORMS VCC (V)
74HC595; 74HCT595
MIN.
TYP.
MAX.
UNIT
52 19 15 55 20 16 47 17 14 47 17 14 41 15 12 17 6 5 11 4 3 17 6.0 5.0 11 4.0 3.0 22 8 7 -6 -2 -2
160 32 27 175 35 30 175 35 30 150 30 26 150 30 26 - - - - - - - - - - - - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2003 Jun 25
13
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
TEST CONDITIONS SYMBOL trem PARAMETER WAVEFORMS removal time MR to SH_CP see Fig.10 VCC (V) 2.0 4.5 6.0 fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4.5 6.0 +50 +10 +9 9 30 35 - - - - - - - - - - - - - - - 95 19 16 95 19 16 95 19 16 65 13 11 95 19 16
74HC595; 74HCT595
MIN.
TYP. -19 -7 -6 30 91 108 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MAX.
UNIT ns ns ns MHz MHz MHz
Tamb = -40 to +85 C tPHL/tPLH propagation delay SH_CP to Q7' see Fig.7 2.0 4.5 6.0 propagation delay ST_CP to An see Fig.8 2.0 4.5 6.0 tPHL propagation delay MR to Q7' see Fig.10 2.0 4.5 6.0 tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 4.5 6.0 tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 4.5 6.0 tW shift clock pulse width HIGH or LOW see Fig.7 2.0 4.5 6.0 storage clock pulse width HIGH or LOW see Fig.8 2.0 4.5 6.0 master reset pulse width LOW see Fig.10 2.0 4.5 6.0 tsu set-up time DS to SH_CP see Fig.9 2.0 4.5 6.0 set-up time SH_CP to ST_CP see Fig.8 2.0 4.5 6.0 200 40 34 220 44 37 220 44 37 190 38 33 190 38 33 - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2003 Jun 25
14
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
TEST CONDITIONS SYMBOL th PARAMETER WAVEFORMS hold time DS to SH_CP see Fig.9 VCC (V) 2.0 4.5 6.0 trem removal time MR to SH_CP see Fig.10 2.0 4.5 6.0 fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4.5 6.0 3 3 3 65 13 11 4.8 24 28 - - - - - - - - - - - - - - - 110 22 19 110 22 19 110 22 19
74HC595; 74HCT595
MIN. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TYP. - - - - - - - - -
MAX.
UNIT ns ns ns ns ns ns MHz MHz MHz
Tamb = -40 to +125 C tPHL/tPLH propagation delay SH_CP to Q7' see Fig.7 2.0 4.5 6.0 propagation delay ST_CP to Qn see Fig.8 2.0 4.5 6.0 tPHL propagation delay MR to Q7' see Fig.10 2.0 4.5 6.0 tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 4.5 6.0 tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 4.5 6.0 tW shift clock pulse width HIGH or LOW see Fig.7 2.0 4.5 6.0 storage clock pulse width HIGH or LOW see Fig.8 2.0 4.5 6.0 master reset pulse width LOW see Fig.10 2.0 4.5 6.0 240 48 41 265 53 45 265 53 45 225 45 38 225 45 38 - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2003 Jun 25
15
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
TEST CONDITIONS SYMBOL tsu PARAMETER WAVEFORMS set-up time DS to SH_CP see Fig.9 VCC (V) 2.0 4.5 6.0 set-up time SH_CP to ST_CP see Fig.8 2.0 4.5 6.0 th hold time DS to SH_CP see Fig.9 2.0 4.5 6.0 trem removal time MR to SH_CP see Fig.10 2.0 4.5 6.0 fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 2.0 4.5 6.0 75 15 13 110 22 19 3 3 3 75 15 13 4 20 24
74HC595; 74HCT595
MIN. - - - - - - - - - - - - - - -
TYP. - - - - - - - - - - - - - - -
MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
2003 Jun 25
16
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Family 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL Tamb = 25 C tPHL/tPLH propagation delay SH_CP to Q7' propagation delay ST_CP to Qn tPHL tPZH/tPZL tPHZ/tPLZ tW propagation delay MR to Q7' 3-state output enable time OE to Qn 3-state output disable time OE to Qn shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW tsu set-up time DS to SH_CP set-up time SH_CP to ST_CP th trem fmax hold time DS to SH_CP removal time MR to SH_CP maximum clock pulse frequency SH_CP or ST_CP see Fig.7 see Fig.8 see Fig.10 see Fig.11 see Fig.11 see Fig.7 see Fig.8 see Fig.10 see Fig.9 see Fig.8 see Fig.9 see Fig.10 see Figs 7 and 8 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 - - - - - 16 16 20 16 16 +3 +10 30 PARAMETER WAVEFORMS VCC (V)
74HC595; 74HCT595
MIN.
TYP.
MAX.
UNIT
25 24 23 21 18 6 5 8 5 8 -2 -7 52
42 40 40 35 30 - - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns ns MHz
Tamb = -40 to +85 C tPHL/tPLH propagation delay SH_CP to Q7' propagation delay ST_CP to Qn tPHL tPZH/tPZL tPHZ/tPLZ propagation delay MR to Q7' 3-state output enable time OE to Qn 3-state output disable time OE to Qn see Fig.7 see Fig.8 see Fig.10 see Fig.11 see Fig.11 4.5 4.5 4.5 4.5 4.5 - - - - - - - - - - 53 50 50 44 38 ns ns ns ns ns
2003 Jun 25
17
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
TEST CONDITIONS SYMBOL tW PARAMETER WAVEFORMS shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW tsu set-up time DS to SH_CP set-up time SH_CP to ST_CP th trem fmax hold time DS to SH_CP removal time MR to SH_CP maximum clock pulse frequency SH_CP or ST_CP see Fig.7 see Fig.8 see Fig.10 see Fig.9 see Fig.8 see Fig.9 see Fig.10 see Figs 7 and 8 VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 20 20 25 20 20 3 13 24
74HC595; 74HCT595
MIN. - - - - - - - -
TYP. - - - - - - - -
MAX.
UNIT ns ns ns ns ns ns ns MHz
Tamb = -40 to +125 C tPHL/tPLH propagation delay SH_CP to Q7' propagation delay ST_CP to Qn tPHL tPZH/tPZL tPHZ/tPLZ tW propagation delay MR to Q7' 3-state output enable time OE to Qn 3-state output disable time OE to Qn shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW tsu set-up time DS to SH_CP set-up time SH_CP to ST_CP th trem fmax hold time DS to SH_CP removal time MR to SH_CP maximum clock pulse frequency SH_CP or ST_CP see Fig.7 see Fig.8 see Fig.10 see Fig.11 see Fig.11 see Fig.7 see Fig.8 see Fig.10 see Fig.9 see Fig.8 see Fig.9 see Fig.10 see Figs 7 and 8 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 - - - - - 24 24 30 24 24 3 15 20 - - - - - - - - - - - - - 63 60 60 53 45 - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns MHz
2003 Jun 25
18
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
AC WAVEFORMS
74HC595; 74HCT595
handbook, full pagewidth
1/fmax
SH_CP input
VM
tW tPLH
tPHL 90%
Q7' output 10% tTLH
VM
tTHL
MSA699
74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the clock (SH_CP) to output (Q7') propagation delays, the shift clock pulse width and maximum shift clock frequency.
handbook, full pagewidth
SH_CP input
VM
tsu
1/fmax
ST_CP input
VM
tW tPLH
tPHL
Qn output
VM
MSA700
74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the storage clock (ST_CP) to output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time.
2003 Jun 25
19
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
handbook, full pagewidth
SH_CP input
VM
tsu th
tsu th
DS input
VM
Q7' output
VM
MLB196
74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.9 Waveforms showing the data set-up and hold times for the DS input.
handbook, full pagewidth
MR input
VM
tW
trem
SH_CP input
VM
tPHL
Q7' output
VM
MLB197
74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the Master Reset (MR) pulse width, the master reset to output (Q7') propagation delay and the master reset to shift clock (SH_CP) removal time.
2003 Jun 25
20
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
handbook, full pagewidth
tr 90% OE input 10% tPLZ Qn output LOW-to-OFF OFF-to-LOW tPHZ Qn output HIGH-to-OFF OFF-to-HIGH outputs enabled outputs disabled 90% VM
tf
tPZL
VM 10% tPZH
VM outputs enabled
MSA697
74HC595: VM = 50%; VI = GND to VCC. 74HCT595: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the 3-state enable and disable times for input OE.
handbook, full pagewidth
VCC VI D.U.T RT CL 50 pF
MGK563
VCC VO RL = 1 k
PULSE GENERATOR
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
SWITCH open VCC GND
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.12 Test circuit for 3-state outputs.
2003 Jun 25
21
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil)
74HC595; 74HCT595
SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 95-01-14 03-02-13
2003 Jun 25
22
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003 Jun 25
23
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 pin 1 index Lp L 1 bp 8 wM detail X A1 (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003 Jun 25
24
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
2003 Jun 25
25
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595; 74HCT595
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 7 vMCAB wM C y1 C
C y
1 Eh 16
8 e 9
15 Dh
10 X 2.5 scale 5 mm
0
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
2003 Jun 25
26
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
74HC595; 74HCT595
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 Jun 25
27
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/04/pp28
Date of release: 2003
Jun 25
Document order number:
9397 750 11263

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